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This site is the home of the "MicroCore" Project.

Micro Core Kernel Architecture

What's new?

  • Report on the use of uCore presented at the 20th euroForth conference 2004

  • MicroCore 120 is released. Get it from the Download page.
    MicroCore 120 uses a SYSCLK twice the uCore clock, getting rid of all asynchronous signals generating precise write clock signals for external data- and/or program-memory. Program memory will be mapped into the I/O-space and therefore, it can be read and written as data van-Neumann-style when needed. A "User Instruction Trap" will be added that allows software emulation of user commands.

What is MicroCore?

The MicroCore team has created a synthesizable VHDL description for a simple yet highly performant micro controller core targeted for synthesis into FPGAs. MicroCore addresses embedded, real-time systems where the user wants full control over both hardware and software and interfaces.

MicroCore is available under license terms which are equivalent to the license terms of the Free Software Foundation. MicroCore aims at empowering the user to modify it according to her/his needs.

MicroCore is a dual-stack, Harvard architecture and its assembler is Forth. MicroCore´s instruction set is independent from its data-path width on an object code level and therefore, its data-path width (and implementation cost) can be adapted to the application needs.

Its Forth cross-compiler is available as well as a C-based instruction simulator. An ANSI-C compiler has been prototyped.

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